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Previously, if we put the following sentence * PLOT v(in) in the simulation->netlist page as an annotated line, the output data cannot be displayed in both the raw data and the graphic format. This problem is solved and n ow the circuit simulations go well with this line in the netlist. |
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Tunneling field-effect-transistors (TFETs) which break the subthreshold swing limit of 60mV/dec in MOSFETs are possible solutions to the power crisis of CMOS. The TFET model here is a surface-potential-based compact model for double-gate (DG) TFETs. Descriptions of both the current-voltage and charge-voltage characteristics are included in this model. |
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Tunneling field-effect-transistors (TFETs) which break the subthreshold swing limit of 60mV/dec in MOSFETs are possible solutions to the power crisis of CMOS. The TFET model here is a surface-potential-based compact model for double-gate (DG) TFETs. Descriptions of both the current-voltage and charge-voltage characteristics are included in this model. |
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The Stanford University CNFET Model is a SPICE-compatible compact model which describes enhancement-mode, unipolar MOSFETs with semiconducting single-walled carbon nanotubes as channels. Each device may have one or more carbon nanotubes with user-specified chirality, and the effects of channel length scaling can be accurately modeled down to 20nm. The model is bas
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The Stanford University CNFET Model is a SPICE-compatible compact model which describes enhancement-mode, unipolar MOSFETs with semiconducting single-walled carbon nanotubes as channels. Each device may have one or more carbon nanotubes with user-specified chirality, and the effects of channel length scaling can be accurately modeled down to 20nm. The model is based on a quasi-ballistic transport picture and includes an accurate description of the capacitor network in a CNFET. It accounts for several practical non-idealities, including the scattering of carriers due to the acoustic and optical phonons in the nanotubes, the parasitic capacitance between the gate and the source/drain formed by multiple 1D nanotubes, the gate-to-gate and gate-to-contact-plug capacitances, the charge screening among the adjacent nanotubes, the access resistance of the source/drain extension regions, the Schottky-barrier resistance at the metal-nanotube contact interfaces, and the band-to-band leakage current. The model has been used to perform circuit-performance comparison with the standard digital library cells between CMOS random logic and CNFET random logic. In addition, by including a full transcapacitance network, it also produces better predictions of the dynamic performance and transient response. The CNFET model can be instantiated directly in SPICE netlists to explore the impacts of CNFETs on the circuit performance. It is an accurate and handy tool for design exploration and verification of CNT circuits.
References
[1] J. Deng and H.-S. P. Wong, "A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application Part I: Model of the Intrinsic Channel Region," IEEE Transactions on Electron Devices, vol. 54, pp. 3186-3194, 2007.
[2] J. Deng, H.-S. P. Wong, “A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application - Part II: Full Device Model and Circuit Performance Benchmarking,” IEEE Trans. Electron Devices, vol. 54, pp. 3195-3205, 2007.
[3] J. Deng and H.-S. P. Wong, "Modeling and Analysis of Planar Gate Capacitance for 1-D FET with Multiple Cylindrical Conducting Channels", IEEE Transactions on Electron Devices, vol. 54, pp. 2377-2385, 2007.
Examples of analyses using the Stanford CNFET SPICE Model
[4] N. Patil, J. Deng, S. Mitra and H.-S. P. Wong, "Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits," IEEE Transactions on Nanotechnology, vol.8, no.1, pp.37-45, Jan. 2009.
[5] J. Zhang, A. Lin, N. Patil, H. Wei, L. Wei, H.-S.P. Wong, and S. Mitra, "Carbon Nanotube Robust Digital VLSI," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31, no.4, pp.453-471, April 2012.
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This model is a surface potential model for carbon nanotube (CNT) FET. Both the ballistic transport and Schottky-barrier effect are incorporated. It is efficient for circuit simulation in large scale. |
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This model is a surface potential model for carbon nanotube (CNT) FET. Both the ballistic transport and Schottky-barrier effect are incorporated. It is efficient for circuit simulation in large scale. |
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This is a surface potential based model for a typical AlGaN HEMTs. An accurate solution from weak inversion, through moderate inversion and finally to strong inversion region is found for the one dimensional (1D) Poisson equation and the Schrodinger equation in the triangular potential. Velocity saturation |
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This is a surface potential based model for a typical AlGaN HEMTs. An accurate solution from weak inversion, through moderate inversion and finally to strong inversion region is found for the one dimensional (1D) Poisson equation and the Schrodinger equation in the triangular potential. Velocity saturation, channel length modulation, drain-induced barrier lower effect, and self-heating effect are included in the presented model. |
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This is a complete charge-based model for ideal silicon nanowire transistor with structure shown in the given figure. Its features include: 1, Inversion charge model from the Poisson's equation in a cylindrical coordinate system
2, Drain current model from the Pao-Sah's dual integral [2]
3, Can be applied to both intr
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This is a complete charge-based model for ideal silicon nanowire transistor with structure shown in the given figure. Its features include: 1, Inversion charge model from the Poisson's equation in a cylindrical coordinate system
2, Drain current model from the Pao-Sah's dual integral [2]
3, Can be applied to both intrinsic body as well has heavily doped body
4, Source/drain charge model included based on the Ward and Dutton's linear charge partition scheme [3]
Missing features:
1, Short channel effects
2, Quantum effects
3, Gate depletion effects
4, Output resistance in saturation
5, Mobility and velocity saturation models
References
[1] F. Liu, J. He, L. Zhang, J. Zhang, J. Hu, C. Ma, and M. Chan, "A Charge-Based Model for Long-Channel Cylindrical Surrounding-Gate MOSFETs From Intrinsic Channel to Heavily Doped Body," IEEE Transactions on Electron Devices, vol. 55, pp. 2187-2194, 2008.
[2] H. C. Pao and C. T. Sah, "Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors," Solid-State Electronics, vol. 9, pp. 927-937, 1966.
[3] D. E. Ward and R. W. Dutton, "A charge-oriented model for MOS transistor capacitances," Solid-State Circuits, IEEE Journal of, vol. 13, pp. 703-708, 1978.
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This is a complete charge-based model for ideal symmetric double MOSFET with structure shown in the given figure. Its features include: 1, Inversion charge model from week inversion to strong inversion calculated from the solution of 1D Poisson-Boltzmann equation [2] in the direction perpendicular to the gate
2, Drain current model from t
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This is a complete charge-based model for ideal symmetric double MOSFET with structure shown in the given figure. Its features include: 1, Inversion charge model from week inversion to strong inversion calculated from the solution of 1D Poisson-Boltzmann equation [2] in the direction perpendicular to the gate
2, Drain current model from the Pao-Sah’s dual integral [3]
3, Can be applied to both intrinsic body as well has heavily doped body
4, Source/drain charge model included based on the Ward and Dutton’s linear charge partition scheme [4]
Missing features:
1, Short channel effects
2, Quantum effects
3, Gate depletion effects
4, Output resistance in saturation
5, Mobility and velocity saturation models
References
[1] L. Zhang, J. Zhang, Y. Song, X. Lin, J. He, and M. Chan, "Charge-based model for symmetric double-gate MOSFETs with inclusion of channel doping effect," Microelectronics Reliability, vol. 50, pp. 1062-1070, 2010.
[2] H. K. Gummel, "A self-consistent iterative scheme for one-dimensional steady state transistor calculations," IEEE Transactions on Electron Devices, vol. 11, pp. 455-465, 1964.
[3] H. C. Pao and C. T. Sah, "Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors," Solid-State Electronics, vol. 9, pp. 927-937, 1966.
[4] D. E. Ward and R. W. Dutton, "A charge-oriented model for MOS transistor capacitances," Solid-State Circuits, IEEE Journal of, vol. 13, pp. 703-708, 1978.
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